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Theory of Operation DMD50 Universal Satellite Modem
3-4 TM118 – Rev. 1.1
Figure 3-3. Universal Satellite Modem Functional Block Diagram
3.1.1 Front Panel
The Front Panel includes a 2 x 16 backlit LCD Display, Indicator LEDs, and a Numeric Keypad
(refer to Section 4.1).
3.1.2 Baseband Processing
The Baseband Processor performs all of the functions required for an IBS/IDR Framing Unit, a
Reed-Solomon Codec, and an E1/T1 Drop and Insert System. In addition, the Baseband
Processing Section provides for transmit clock selection and rate adaptation as well as a rate
adapter and Plesiochronous/Doppler (PD) Buffer in the receive direction. A multiplexer is also
provided for the SCT Clock Source for Loop Timing Applications. The transmit and receive paths
may be configured independently under processor control.
- Universal Satellite Modem 1
- Warranty Policy 4
- Preface 6
- Trademarks 7
- Copyright 7
- Disclaimer 7
- Record of Revisions 7
- Table of Contents 8
- TM118 – Rev. 1.1 ix 10
- TM118 – Rev. 1.1 xi 12
- TM118 – Rev. 1.1 xiii 14
- TM118 – Rev. 1.1 xv 16
- Introduction 18
- 1-2 TM118 – Rev. 1.1 19
- TM118 – Rev. 1.1 1-3 20
- Installation 22
- 2.1 Unpacking 23
- 2.2 Removal and Assembly 23
- 2.3 Mounting Considerations 24
- 2-4 TM118 – Rev. 1.1 25
- 2.5 Modulator Checkout 26
- 2.5.1 Initial Power-Up 26
- 2.6 Storage 26
- 2-6 TM118 – Rev. 1.1 27
- Theory of Operation 28
- 3-2 TM118 – Rev. 1.1 29
- 3.1.1 Front Panel 31
- 3.1.2 Baseband Processing 31
- 3.2.1 Terminal Port 33
- 3.2.3 Ethernet M&C Port 33
- 3.2.4 Modem Monitor Status 33
- 3.4 Internal Clock 34
- TM118 – Rev. 1.1 3-9 36
- 3-10 TM118 – Rev. 1.1 37
- 3.6 Clocking Options 38
- 3.6.1 TX Clock Options 38
- TM118 – Rev. 1.1 3-13 40
- 3-14 TM118 – Rev. 1.1 41
- TM118 – Rev. 1.1 3-15 42
- 3-16 TM118 – Rev. 1.1 43
- TM118 – Rev. 1.1 3-17 44
- 3-18 TM118 – Rev. 1.1 45
- TM118 – Rev. 1.1 3-19 46
- 3.12 ESC Backward Alarms 47
- TM118 – Rev. 1.1 3-21 48
- 3.13.2 Aggregate Data Rate 49
- (less than In-Band Rate) 50
- 3-24 TM118 – Rev. 1.1 51
- 3.16 Strap Codes 52
- 3-26 TM118 – Rev. 1.1 53
- User Interfaces 54
- 4.1.3 Numeric Keypad 55
- 4.2 Parameter Setup 56
- 4.3.1 Main Menus 57
- TM118 – Rev. 1.1 4-5 58
- 4-6 TM118 – Rev. 1.1 59
- TM118 – Rev. 1.1 4-7 60
- 4-8 TM118 – Rev. 1.1 61
- TM118 – Rev. 1.1 4-9 62
- 4-10 TM118 – Rev. 1.1 63
- TM118 – Rev. 1.1 4-11 64
- 4-12 TM118 – Rev. 1.1 65
- TM118 – Rev. 1.1 4-13 66
- 4-14 TM118 – Rev. 1.1 67
- TM118 – Rev. 1.1 4-15 68
- 4-16 TM118 – Rev. 1.1 69
- TM118 – Rev. 1.1 4-17 70
- Only these will 71
- Will not be 71
- 4>3 and 5>3 71
- TM118 – Rev. 1.1 4-19 72
- 4-20 TM118 – Rev. 1.1 73
- TM118 – Rev. 1.1 4-21 74
- 4-22 TM118 – Rev. 1.1 75
- TM118 – Rev. 1.1 4-23 76
- 4-24 TM118 – Rev. 1.1 77
- TM118 – Rev. 1.1 4-25 78
- 4-26 TM118 – Rev. 1.1 79
- TM118 – Rev. 1.1 4-27 80
- 4-28 TM118 – Rev. 1.1 81
- TM118 – Rev. 1.1 4-29 82
- distant satellite end 83
- TM118 – Rev. 1.1 4-31 84
- 4-32 TM118 – Rev. 1.1 85
- TM118 – Rev. 1.1 4-33 86
- 4-34 TM118 – Rev. 1.1 87
- TM118 – Rev. 1.1 4-35 88
- 4-36 TM118 – Rev. 1.1 89
- TM118 – Rev. 1.1 4-37 90
- 4-38 TM118 – Rev. 1.1 91
- TM118 – Rev. 1.1 4-39 92
- 4-40 TM118 – Rev. 1.1 93
- 4.4 Terminal Mode Control 94
- 4.6 Connecting the Terminal 95
- 4.7 Terminal Screens 95
- 4.8.1 Protocol Structure 96
- 4-44 TM118 – Rev. 1.1 97
- Rear Panel Interfaces 98
- 5-2 TM118 – Rev. 1.1 99
- 5.3.5 RX L-Band IF (J14) 100
- 5.3.6 ALARM (J15) 100
- 5.3.7 EXT CLK (J16) 100
- 5.3.8 ASYNC (J17) 101
- 5.3.9 J18 101
- 5.3.10 EIA-530 (J19) 101
- 5.3.11 REMOTE (J20) 102
- 5.3.12 ETHERNET (J21) 103
- 5.4.1 ESC ALARM (J1) 103
- 5.4.2 64K AUDIO (J2) 104
- 5.4.3 8K DATA (J3) 105
- 5.4.4 G.703 BAL (J4) 105
- 5.4.5 SWITCH INTERFACE (J5) 106
- 5-10 TM118 – Rev. 1.1 107
- TM118 – Rev. 1.1 5-11 108
- 5.4.6 SD (DDI) (J6) 109
- 5.4.7 DDO (J7) 109
- 5.4.8 IDI (J8) 109
- 5.4.9 SD (IDO) (J9) 109
- 5.6.1 HSSI (J6) 110
- 5.7.1 ASI IN (J1) 111
- 5.7.2 ASI OUT (J2) 111
- 5.7.3 DVB/M2P IN (J3) 111
- TM118 – Rev. 1.1 5-15 112
- 5.7.4 DVB/M2P OUT (J4) 113
- TM118 – Rev. 1.1 5-17 114
- 5.9 HSSI / G.703 115
- 5.9.1 64K AUDIO (J2) 116
- 5.9.2 8K DATA (J3) 117
- 5.9.3 G.703 BAL (J4) 118
- 5.9.4 ESC ALARM (J5) 119
- 5.9.5 SD (DDI) (J6) 119
- 5.9.6 DDO (J7) 119
- 5.9.7 IDI (J8) 120
- 5.9.8 SD (IDO) (J9) 120
- 5.10 HSSI / Ethernet (J1) 120
- 5.12 GigE Interface 121
- TM118 – Rev. 1.1 5-25 122
- 6.0 Periodic Maintenance 124
- 6.0.1 Clock Adjustment 124
- 6.1 Troubleshooting 124
- 6.1.1 Alarm Faults 125
- 6.1.1.1 Major Tx Alarms 125
- 6.1.1.2 Major Rx Alarms 126
- 6.1.1.3 Minor Tx Alarms 126
- 6.1.1.4 Minor Rx Alarms 127
- 6.1.1.6 Common Major Alarms 128
- 6-6 TM118 – Rev. 1.1 129
- 6.1.2.3 Backward Alarms 130
- 6-8 TM118 – Rev. 1.1 131
- TM118 – Rev. 1.1 6-9 132
- Technical Specifications 134
- 7.2 Demodulator 135
- 7.3 Plesiochronous Buffer 135
- 7.4 Monitor and Control 135
- TM118 – Rev. 1.1 7-3 136
- 7-4 TM118 – Rev. 1.1 137
- 7.18 Data Rate Limits 138
- 7.18.1 Non-DVB 138
- 7.18.2 DVB 139
- TM118 – Rev. 1.1 7-7 140
- Viterbi 141
- Sequential 142
- Viterbi Decoder 143
- Reed Solomon 143
- Turbo Decoder 144
- 7-12 TM118 – Rev. 1.1 145
- Trellis 147
- TM118 – Rev. 1.1 7-15 148
- 7-20 TM118 – Rev. 1.1 153
- TM118 – Rev. 1.1 7-21 154
- 7-22 TM118 – Rev. 1.1 155
- TM118 – Rev. 1.1 7-23 156
- 7.18.13 AGC Output Voltage 157
- TM118 – Rev. 1.1 7-25 158
- Product Options 160
- TM118 – Rev. 1.1 A-3 162
- B.0 Introduction 164
- B.1 Required Equipment 164
- B.2 Upgrade Procedure 164
- B-2 TM118 – Rev. 1.1 165
- B.3 Demonstration Procedure 166
- B-4 TM118 – Rev. 1.1 167
- TM118 – Rev. 1.1 168
- B-6 TM118 – Rev. 1.1 169
- Carrier Control 172
- C.5 Carrier RTS 173
- TM118 – Rev. 1.1 C-3 174
- Strap Codes 176
- D.1 Sample Applications 179
- TM118 – Rev. 1.1 D-5 180
- D-6 TM118 – Rev. 1.1 181
- TM118 – Rev. 1.1 D-7 182
- Case 4: Loop Timing Example 183
- TM118 – Rev. 1.1 D-9 184
- TCP/IP Ethernet Setup 186
- E.3 Ethernet Test 188
- Network) 188
- E-4 TM118 – Rev. 1.1 189
- TM118 – Rev. 1.1 E-5 190
- E-6 TM118 – Rev. 1.1 191
- TM118 – Rev. 1.1 E-7 192
- Web Browser Setup Guide 194
- F-2 TM118 – Rev. 1.1 195
- TM118 – Rev. 1.1 F-3 196
- F.2 Modem Web Site 197
- F.3 Web Page Appearance 198
- F-6 TM118 – Rev. 1.1 199
- TM118 – Rev. 1.1 F-7 200
- AUPC Operation 202
- G-2 TM118 – Rev. 1.1 203
- TM118 – Rev. 1.1 G-3 204
- G-4 TM118 – Rev. 1.1 205
- Drop and Insert (D&I) 206
- H-2 TM118 – Rev. 1.1 207
- H.0.1 Drop Only 208
- H.0.2 Insert Only 208
- H-4 TM118 – Rev. 1.1 209
- H.0.3 Mode Selection 210
- H.0.3.1 PCM-30 210
- H.0.3.2 PCM-30C 210
- H.0.3.3 PCM-31 210
- H.0.3.4 PCM-31C 210
- H.0.3.5 T1-D4/T1-D4-S 211
- H.0.3.6 T1-ESF/T1-ESF-S 211
- TM118 – Rev. 1.1 H-7 212
- H-8 TM118 – Rev. 1.1 213
- H.1.1 Data Rate 214
- H-10 TM118 – Rev. 1.1 215
- TM118 – Rev. 1.1 H-11 216
- H-12 TM118 – Rev. 1.1 217
- TM118 – Rev. 1.1 H-13 218
- H-14 TM118 – Rev. 1.1 219
- TM118 – Rev. 1.1 H-15 220
- H-16 TM118 – Rev. 1.1 221
- TM118 – Rev. 1.1 H-17 222
- H-18 TM118 – Rev. 1.1 223
- TM118 – Rev. 1.1 H-19 224
- Efficient Drop & Insert 226
- I-2 TM118 – Rev. 1.1 227
- TM118 – Rev. 1.1 I-3 228
- I-4 TM118 – Rev. 1.1 229
- TM118 – Rev. 1.1 I-5 230
- I-6 TM118 – Rev. 1.1 231
- Glossary 232
- J-2 TM118 – Rev. 1.1 233
- J-4 TM118 – Rev. 1.1 235
- J-6 TM118 – Rev. 1.1 237
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